Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

Multi-chip semiconductor device and method for making the device by using multiple flip chip interfaces

Abstract: A bump-bonded multi-chip flip-chip device (100) is formed by manufacturing a mother chip (102) having a first set (207) of bumps (212) and a second set (209) of bump contacts (210). A daughter chip (104) is also formed which has conductive bumps (312). The daughter chip (104) and the mother chip (102) are placed face-to-face and contact is made between the daughter chips bumps (312) and the mother chips bump contact regions (210). After interconnection of the daughter chip (104) and the mother chip (102), the mother chip (102) is contacted to an IC package (106) using the bumps (212). The package (106) uses a plurality of metallic layers interconnected selectively by conductive vias in order to route signals between the mother chip (102), the daughter chip (104), and external terminals (112) of the package (106).

Pad array semiconductor device

Abstract: Pad array carriers allow greater I/O densities over conventional leaded packages by using an array arrangement for external electrical connections. A pad array carrier (48) is manufactured using a substrate (40) having metal on only one side and unplated through-holes (44). A semiconductor die (50) is mounted on and affixed to the top surface of the substrate with an electrically insulative adhesive (51). The use of the insulative adhesive allows routing of signal traces into the die mounting region directly underneath the die. Wire bonds (52) connect the die to metal traces (46) on the substrate. A package body (54) is formed on the substrate covering the die and wire bonds (52). Solder balls (56 & 58) are directly attached to the backside of the solder pads (47) by way of the through-holes.

Method of forming vias through two-sided substrate

Abstract: An integrated circuit substrate (26) is formed with active circuit elements (24, 32) on first and second surfaces of the substrate. The active circuit elements are interconnected with though-substrate vias (28) to minimize signal routing and reduce propagation delay. The through-substrate vias may be formed with a plurality of holes (52) through the IC substrate. A dielectric layer (54) is deposited on the surface of the IC substrate and through the holes. A conductive layer (56) is deposited through the holes to form the through-substrate vias. The dielectric layer is removed from the surface of the IC substrate to leave the through-substrate vias isolated from the IC substrate by the dielectric layer. A second substrate (26) is formed as described and the two substrates are joined as a two-sided chip (21) with active circuit elements on both sides interconnected by through-substrate vias.

Split-gate memory device and method for accessing the same

Abstract: An EEPROM device includes a split-gate FET (10) having a source (36), a drain (22), a select gate (16) adjacent the drain (22), and a control gate (32) adjacent the source (36). When programming the split-gate FET (10), electrons are accelerated in a portion of a channel region (38) between the select gate (16) and the control gate (32), and then injected into a nitride layer (24) of an ONO stack (25) underlying the control gate (32). The split-gate FET (10) is erased by injecting holes from the channel region (38) into the charge nitride layer (24). When reading data from the split-gate FET (10), a reading voltage is applied to the drain (22) adjacent the select gate (16). Data is then read from the split-gate FET (10) by sensing a current flowing in a bit line coupled to the drain (22).

CVD reactor with uniform layer depositing ability

Abstract: A CVD reactor with a flat generally rectangularly shaped susceptor having a leading edge including a curve which is concave in the direction of gas flow through the reactor. The reactor produces epitaxial layers on semiconductor wafers in which the uniformity of the layer is dependent upon the radius of the concave curvature.