Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

Methods and apparatus for EMI shielding in multi-chip modules

Abstract: Methods and structures provide a shielded multi-layer package for use with multi-chip modules and the like. A substrate (102) (e.g., chip carrier) has an adhesive layer (104), where electronic components (106, 108) are attached. An insulating layer (110) is formed over the plurality of electronic components, and a conductive encapsulant structure (115) is formed over the insulating layer. The adhesive layer is detached from the electronic components, and multi-layer circuitry (140) is formed over, and in electrical communication with, the plurality of electronic components. A shielding via (150) is formed through the multilayer circuitry such that it contacts the conductive encapsulant.

Ultra wideband communication system, method, and device with low noise reception

Abstract: An ultra-wide band (UWB) waveform receiver with noise cancellation for use in a UWB digital communication system. The UWB receiver uses a two-stage mixing approach to cancel noise and bias in the receiver. Self-jamming is prevented by inverting a portion of the received signal in the first mixer and then coherently detecting the partially and synchronously inverted signal in the second mixer. Since the drive signals on both mixers are not matched to the desired signal, leakage of either drive signal does not jam the desired signal preventing the receiver from detecting and decoding a weak signal.

Method of identifying an improved configuration for a communication system using coding gain and an apparatus therefor

Abstract: Coding gain is used to configure a communication system using a programmable error correction scheme. A best available error correction configuration is selected from among several configurations to provide an optimal coding gain performance for a given line or set of line characteristics and a given communication system. Payload is calculated for each of several error correction configurations, and the configuration providing the highest payload for a target bit error rate is selected. Use of gross gain to configure the communication system further provides an optimal configuration.

Electrical impact of line-edge roughness on sub-45-nm node standard cells

Abstract: Since line-end roughness (LER) has been reported to be of the order of several nanometers and to not decrease as the device shrinks, it has evolved as a critical problem in sub-45-nm devices and may lead to serious device parameter fluctuations and performance limitations for future very large scale integration (VLSI) circuit applications. We present a new cell characterization methodology that uses the nonrectangular gate print images generated by lithography and etch simulations with the random LER variation. We systematically analyze the random LER by taking the impact on circuit performance due to LER variation into consideration. We observed that the saturation current, delay, and leakage current are highly affected by LER as the gate length becomes thinner. Results show that when the root mean square value of LER is 6 nm from its nominal line edge, the worst case saturation current, delay, and leakage current degradation are as much as 10.3% decrease, 12.4% increase, and 7× increase at a 45-nm-node standard cell. Meanwhile the current, delay, and leakage current degradation at a 32-nm-node cell are up to 19.0% decrease, 21.8% increase, and 4600× increase, respectively.

Package on Package warpage - impact on surface mount yields and board level reliability

Abstract: The need to integrate devices in the vertical dimension to reduce space, thickness, and cost for handheld applications has fueled the enormous growth of what can be termed 3D packaging. Due to testability, business flow, and configuration flexibility issues, the package on package (PoP) vertical stacking solution has emerged as the preferred method to stack mobile phone logic processor with memory. The PoP solution typically consists of the logic processor in the bottom package and memory device stack in the top package. The bottom PoP has land pads on the top perimeter in order to allow top PoP to be mounted and reflowed above. Both packages must be capable of being placed on the printed circuit board (PCB) and reflowed simultaneously to each other and to the board. Hence the warpage of the top and bottom PoP relative to each other becomes critical in impacting board mount yields and adoption. This paper presents a systematic study performed to modulate the warpage of the top as well as the bottom PoP and study the effect of the relative warpage of the top and bottom PoP on surface mount (SMT) yields during PoP assembly. A 15times15 mm POP module was selected for this study. This package size represents the higher side of the typical package size spectrum for PoP applications and hence the warpage effects are also magnified. Shadow Moire technique was used for high temperature warpage measurement while subjecting the test samples to a simulated reflow profile. The results of this study can be used as a reference by original equipment manufacturers (OEMs) to define warpage limits to ensure a robust SMT POP stacking yield and board level reliability of the POP module. Further, it can used by integrated device manufacturers (IDMs) and packaging subcontractors to determine the kind of material set and construction required to meet specific warpage targets and be compatible with the other package in the PoP stack. This represents a significant advancement over the current practice of procuring the top and bottom packages manufactured independent of each other and reactively dealing with SMT yield issues.