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Institution

Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..


Papers
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Patent
04 Dec 1989
TL;DR: In this paper, a multifunction ground plane for an electrical device such as an integrated circuit (11) is provided by a plurality of conductors (14) each having one end thereof adapted to be coupled to the electrical device (11), with a ground plane (20) adjacent and electrically isolated (16) from said plurality of conducting devices (14).
Abstract: A multifunction ground plane for an electrical device such as an integrated circuit (11) is provided by a plurality of conductors (14) each having one end thereof adapted to be coupled to the electrical device (11) with a ground plane (20) adjacent and electrically isolated (16) from said plurality of conductors (14). The ground plane (20) includes a plurality of electrically isolated portions (21) each of which can be coupled to the electrical device (11) to provide operating potential (V) and/or signals thereto or therefrom. The isolated ground plane portions (21) have an impedance less than that of the electrical conductors (14) and provide an alternate means for connecting operating potential(s) (V) and/or operating signals to and from the electrical device (11) while still functioning as a ground plane for the electrical conductors (14).

38 citations

Patent
03 May 1994
TL;DR: In this article, a dual absolute pressure sensor independently converts first and second external pressures to the electrical signals, respectively, using a first cavity having a reference pressure to measure against the first external pressure and develop a first differential pressure.
Abstract: A dual absolute pressure sensor independently converts first and second external pressures to first and second electrical signals respectively. A package body has first and second openings for receiving the first and second external pressures to outside surfaces of first and second sensor die attached to opposite surfaces of an internal glass substrate that separates the first and second openings. The first sensor die includes a first cavity having a reference pressure to measure against the first external pressure and develop a first differential pressure. A first piezoelectric network converts the first differential pressure to the first electrical signal representative of that pressure. The second sensor die includes a second cavity having a reference pressure to independently measure against the second external pressure and develop a second differential pressure. A second piezoelectric network converts the second differential pressure to the second electrical signal representative of that pressure.

38 citations

Patent
15 Mar 2006
TL;DR: In this paper, a method of scheduling execution of a plurality of tasks by a processor, the processor having a processor memory, the processors being arranged to load into the processor memory during execution of current tasks, data for a task that is scheduled for execution after the processor has completed the current task, is presented.
Abstract: A method of scheduling execution of a plurality of tasks by a processor, the processor having a processor memory, the processor being arranged to load into the processor memory, during execution of a current task, data for a task that is scheduled for execution after the processor has completed the current task, the method comprising the steps of: scheduling a next task for execution by the processor after the processor has completed a current task; and determining whether there is a high priority task to be executed by' the processor; the method being characterized by the steps of: if there is a high priority task to be executed by the processor: determining whether the processor has begun loading the data for the next task into the processor memory; and if the processor has not begun loading the data for the next task into the processor memory, scheduling the high priority task, instead of the next task, for execution by the processor after the processor has completed the current task.

38 citations

Patent
30 Dec 2003
TL;DR: In this paper, an adaptive analog-to-digital converter (ADC) system includes an automatic gain control (AGC) controller for receiving both in-band and out-of-band signals from a radio frequency (RF) receiver and producing an AGC control signal therefrom.
Abstract: An adaptive analog-to-digital converter (ADC) system ( 100 ) includes an automatic gain control (AGC) controller ( 101 ) for receiving both in-band and out-of-band signals from a radio frequency (RF) receiver and producing an AGC control signal therefrom. A digital signal processor (DSP) ( 103 ) is then used for interpreting the AGC control signal and providing an adjustment signal to an ADC ( 105 ). The ADC ( 105 ) uses the adjustment signal to dynamically control efficiency of the ADC system 100 by adjusting bit resolution, reference capacitance and bias based upon the RF signal received and desired protocol requirements presented to the AGC controller ( 101 ).

38 citations

Patent
01 Sep 1998
TL;DR: In this paper, a method of forming a thin silicide layer on a silicon substrate was proposed, which includes heating the surface of the substrate to a temperature of approximately 500° C. to 750° C and directing an atomic beam of silicon and an alkaline-earth metal at the heated surface in a molecular beam epitaxy chamber at a pressure in a range below 10-9 Torr.
Abstract: A method of forming a thin silicide layer on a silicon substrate 12 including heating the surface of the substrate to a temperature of approximately 500° C. to 750° C. and directing an atomic beam of silicon 18 and an atomic beam of an alkaline-earth metal 20 at the heated surface of the substrate in a molecular beam epitaxy chamber at a pressure in a range below 10-9 Torr. The silicon to alkaline-earth metal flux ratio is kept constant (e.g. Si/Ba flux ratio is kept at approximately 2:1) so as to form a thin alkaline-earth metal silicide layer (e.g. BaSi2) on the surface of the substrate. The thickness is determined by monitoring in situ the surface of the single crystal silicide layer with RHEED and terminating the atomic beam when the silicide layer is a selected submonolayer to one monolayer thick.

38 citations


Authors

Showing all 7673 results

NameH-indexPapersCitations
David Blaauw8775029855
Krishnendu Chakrabarty7999627583
Rajesh Gupta7893624158
Philippe Renaud7777326868
Min Zhao7154724549
Gary L. Miller6330613010
Paul S. Ho6047513444
Ravi Subrahmanyan5935314244
Jing Shi5322210098
A. Alec Talin5231112981
Chi Hou Chan485119504
Lin Shao4838012737
Johan Åkerman483069814
Philip J. Tobin471866502
Alexander A. Demkov473317926
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Performance
Metrics
No. of papers from the Institution in previous years
YearPapers
20211
20203
201910
201826
201779
2016267