Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

High Speed Gallium Nitride Transistor Devices

Abstract: A low leakage current switch device (110) is provided which includes a GaN-on-Si substrate (11-13) covered by a passivation surface layer (43) in which a T-gate electrode with sidewall extensions (48) is formed and coated with a conformal passivation layer (49) so that the T-gate electrode sidewall extensions are spaced apart from the underlying passivation surface layer (43) by the conformal passivation layer (49).

Partially Depleted Dielectric Resurf LDMOS

Abstract: An partially depleted Dieler LDMOSFET transistor ( 100 ) is provided which includes a substrate ( 150 ), a drift region ( 110 ) surrounding a drain region ( 128 ), a first well region ( 107 ) surrounding source region ( 127 ), a well buffer region ( 106 ) separating the drift region and first well region to at least partly define a first channel region, a gate electrode ( 118 ) formed over the first channel region having a source-side gate edge aligned with the first well region ( 107 ), an LDD extension region ( 120 ) extending from the source region to the channel region, and a dielectric RESURF drain extension structure ( 161 ) formed at the drain of the gate electrode ( 118 ) using the plurality of STI stripes ( 114 ).

High reliability output buffer for multiple voltage system

Abstract: An output buffer (30) is connected to an output signal line and receives an internal power supply voltage, for example 3.3 volts, which is lower than a voltage, for example 5 volts, that other devices which may be connected to the output signal line are able to drive. To protect an output transistor (71) from the harmful effects of the higher voltages on the output signal line, the output buffer (30) includes a special bulk biasing circuit (80). The bulk biasing circuit (80) biases the bulk of the output transistor (71) at an internal power supply voltage when the output buffer is driving and when not driving to a voltage determined by the output signal. To prevent overlap currents, the output buffer (30) includes a special gate biasing circuit (100), which momentarily drives the gate of the output transistor (71) to a voltage equal to the internal power supply voltage when the output buffer (30) stops driving.

Automotive radar system and method for using same

Abstract: A radar system (44) for a vehicle (42) includes a transmit unit (56) and a receive unit (58). The transmit unit (56) includes a single beam antenna (72) for output of a radar signal (74) into a target zone (46). The receive unit (58) includes a single beam antenna (76) for receiving a direct receive signal (78) and an indirect receive signal (80). The receive signals (78, 80) are reflections of the radar signal (74) from an object (34, 36) in the target zone (46). The indirect receive signal (80) is reflected off the object (34, 36) toward a reflective panel (54) of the vehicle (42), and the indirect receive signal (80) is reflected off the reflective panel (54) for receipt at the receive antenna (76). The receive signals (78, 80) are summed to produce a detection signal (81) indicating presence of the object (34, 36) in the target zone (46).

Data processor a method and apparatus for performing postnormalization in a floating-point execution unit

Abstract: A method and apparatus for performing prenormalization during execution by an execution unit (100) of a floating-point add/subtract operation using two data operands. The execution unit (100) adds a mantissa portion of a first and a second floating-point data operand to generate a prenormalized mantissa sum. The execution unit (100) minimizes critical path delays to allow high-performance floating-point calculations while simultaneously reducing logic. Instead of treating the prenormalized mantissa sum as a 64-bit value with special treatment in case of a carry out due to overflow, the floating-point adder 100 treats the prenormalized mantissa sum as a 65-bit value, with the most significant bit being a carry output. Instead of conditionally incrementing an initial exponent value, the initial exponent value is always incremented. Thus, allowing the floating-point adder unit 100 to perform the exponent adjustments for normalization and for rounding faster.