Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

In a data processor a method and apparatus for performing a floating-point comparison operation

Abstract: A data processor (10) has a floating-point execution unit (32) for executing a floating-point compare operation using two data operands. The execution unit (32) uses mantissa comparator logic (107) to perform a bit-wise comparison of a mantissa portion of a first operand with the mantissa portion of a second operand, and to provide a mantissa comparison result. Similarly, exponent comparator logic (122) performs a bit-wise comparison of an exponent portion of the first operand with the exponent portion of the second, and provides an exponent comparison result. Comparator logic (114) in the execution unit receives the mantissa comparison result and the exponent comparison result. If the exponent portions of the two operands are not equal, the comparator logic (114) uses an operand sign bit of each operand and the exponent comparison result to order the two operands. If the exponent portions of the two operands are equal, the comparator logic uses the operand sign bit of each operand and the mantissa comparison result to order the two operands.

Statistical analysis of electromigration lifetimes and void evolution

Abstract: Electromigration failure statistics and the origin of the log-normal standard deviation for copper interconnects were investigated by analyzing the statistics of electromigration lifetime and void size distributions at various stages during testing. Experiments were performed on 0.18μm wide Cu interconnects with tests terminated after certain amounts of resistance increase, or after a specified test time. The lifetime and void size distributions were found to follow log-normal distribution functions. The sigma values of these distributions decrease with increasing test time. The statistics of resistance-based void size distributions can be simulated by considering geometrical variations of the void shape. In contrast, the characteristics of time-based void size distributions require consideration of kinetic aspects of the electromigration process. The sigma values of lifetime distributions can be adequately simulated by combining the statistics of both types of void size distributions. Thus, a statistical...

Heterojunction interband tunnel diodes with improved P/V current ratios

Abstract: A heterojunction tunnel diode with first and second barrier layers, the first barrier layer including aluminum antimonide arsenide. A quantum well formation is sandwiched between the first and second barrier layers, and includes first and second quantum well layers with a barrier layer sandwiched therebetween, the first quantum well layer being adjacent the first barrier layer. The first quantum well layer is gallium antimonide arsenide which produces a peak in hole accumulations therein. The second quantum well layer produces a peak in electron accumulations therein. A monolayer of gallium antimonide is sandwiched in the first quantum well layer at the peak in hole accumulations and a monolayer of indium arsenide is sandwiched in the second quantum well layer at the peak in electron accumulations.

High frequency linear amplifier assembly

Abstract: A wide bandwidth linear amplifier (10) that has an operating band in excess of 1 GHz mounts the high power dissipating components (11) of the amplifier (10), and the components 917, 18) that control the high frequency gain and stability of the amplifier (10) onto a daughter board (32) that has a high thermal conductivity The daughter board (32) and the remaining circuit components (21, 22, 23, 24, 26a, 26b) are then mounted on a mother board (31) that has a lower thermal conductivity The assembly (30) reduces the circuit's parasitic inductance (46, 47, 48, 49) and parasitic capacitance (51, 52), and provides unconditional stability at high frequencies

BiCMOS device having an SOI substrate and process for making the same

Abstract: A BiCMOS device and process are disclosed wherein the transistors components are fabricated on an SOI substrate. A SIMOX process is used to form a buried oxide layer in a single crystal silicon substrate followed by an epitaxial deposition to form a silicon body of varying thickness overlying the buried oxide layer. MOS transistors are then formed in a thin portion of the epitaxial layer and a vertical bipolar transistor is formed in the thick portion of the epitaxial layer. In accordance with one embodiment of the invention, a single crystal semiconductor substrate is provided having a principal surface and a buried oxide layer underlying the first surface. A lightly doped epitaxial layer of a first conductivity type having a thin MOS region and a thick bipolar region overlies the principal surface. A first and second isolation regions extending from the first surface to the buried oxide layer separate and electrically insulate the bipolar region from the MOS region. An NMOS and a PMOS transistor are formed in the thin MOS region and are separated by a third isolation region extending from the first surface to the buried oxide layer. A vertical bipolar is formed in the electrically insulated bipolar region of the epitaxial layer.