Institution
Freescale Semiconductor
About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..
Topics: Layer (electronics), Signal, Transistor, Integrated circuit, Voltage
Papers published on a yearly basis
Papers
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03 Apr 1998TL;DR: A branch prediction unit apparatus and method uses an instruction buffer (20), a completion unit (24), and a branch prediction units (28) as discussed by the authors, which are used to perform efficient branch prediction, branch resolution/retirement, and branch misprediction recovery.
Abstract: A branch prediction unit apparatus and method uses an instruction buffer (20), a completion unit (24), and a branch prediction unit (BPU) (28). The instruction buffer (20) and/or the completion unit (24) contain a plurality of instruction entries that contain valid bits and stream identifier (SID) bits. The branch prediction unit contains a plurality of branch prediction buffers (28a-28c). The SID bits are used to associate the pending and executing instructions in the units (20 and 24) into instruction streams related to predicted branches located in the buffers (28a-28c). The SID bits as well as age bits associated with the buffers (28a-28c) are used to perform efficient branch prediction, branch resolution/retirement, and branch misprediction recovery.
40 citations
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29 Mar 1996TL;DR: In this paper, a Schottky diode is fabricated by growing a dielectric film on a SiC substrate structure and forming an ohmic contact on the opposite surface of the substrate structure by depositing a layer of metal and annealing at a temperature above 900° C.
Abstract: Fabricating a device including a Schottky diode by growing a dielectric film on a SiC substrate structure and forming an ohmic contact on the opposite surface of the substrate structure by depositing a layer of metal and annealing at a temperature above 900° C. Implanting doping material in the substrate structure through spaced apart openings to form high resistivity areas and depositing a dielectric layer on the dielectric film to define a contact opening positioned between the spaced apart high resistivity areas. Annealing the implant at a temperature less than approximately 400° C. to reduce reverse leakage current and depositing metal in the contact opening to form a Schottky contact.
40 citations
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29 Apr 2005TL;DR: In this article, a test access port receives an external testing signal from a source outside the semiconductor device, and an on-chip test module (e.g., a built-in self-test (BIST) module) contained within the device provides an internal testing signal for the system logic.
Abstract: Semiconductor devices, circuits and methods apply both system logic tests and external interface tests via a common series of boundary shift registers residing on the semiconductor chip. In an exemplary embodiment, a test access port receives an external testing signal from a source outside the semiconductor device, and an on-chip test module (e.g. a built-in self-test (BIST) module) contained within the semiconductor device provides an internal testing signal for the system logic. Control logic selectively provides appropriate input testing signals to the boundary shift registers and receives and processes appropriate output signals from the boundary shift registers in each testing mode. Using the various control techniques, a common set of boundary scan registers may be used to implement, for example, an IEEE 1149.1 interface, a BIST isolation wrapper scan chain, a BIST-mode input/output control, or the like.
39 citations
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13 Jan 2010TL;DR: In this article, an IC device (202) is configured to temporarily enable access to a debug interface (216) of the IC device via authentication of the first party by a challenge/response process using a key (321, 322) and a challenge value (324) generated at the IC devices (202).
Abstract: Under the direction of a first party, an integrated circuit (IC) device (202) is configured to temporarily enable access to a debug interface (216) of the IC device (202) via authentication of the first party by a challenge/response process using a key (321, 322) of the IC device (202) and a challenge value (324) generated at the IC device (202). The first party then may conduct a software evaluation of the IC device (202) via the debug interface (216). In response to failing to identify an issue with the IC device (202) from the software evaluation, the first party can permanently enable open access to the debug interface (216) while authenticated and provide the IC device (202) to a second party. Under the direction of the second party, a hardware evaluation of the IC device (202) is conducted via the debug interface (216) that was permanently opened by the first party.
39 citations
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08 Oct 1992TL;DR: In this paper, a CMOS device and a method for its fabrication is described, which includes an NMOS transistor and a PMOS transistor each of which has silicided source and drain regions and a silicon gate electrode which includes a titanium nitride barrier layer.
Abstract: A CMOS device and a method for its fabrication are disclosed. In one embodiment the CMOS device includes an NMOS transistor and a PMOS transistor each of which has silicided source and drain regions and a silicon gate electrode which includes a titanium nitride barrier layer. The NMOS transistor and PMOS transistors are coupled together by a silicon layer which is capped by a layer of titanium nitride barrier material. The source and drain regions are silicided with cobalt or other metal silicide which is prevented from reacting with the silicon gate electrode and interconnect by the presence of the titanium nitride barrier layer.
39 citations
Authors
Showing all 7673 results
Name | H-index | Papers | Citations |
---|---|---|---|
David Blaauw | 87 | 750 | 29855 |
Krishnendu Chakrabarty | 79 | 996 | 27583 |
Rajesh Gupta | 78 | 936 | 24158 |
Philippe Renaud | 77 | 773 | 26868 |
Min Zhao | 71 | 547 | 24549 |
Gary L. Miller | 63 | 306 | 13010 |
Paul S. Ho | 60 | 475 | 13444 |
Ravi Subrahmanyan | 59 | 353 | 14244 |
Jing Shi | 53 | 222 | 10098 |
A. Alec Talin | 52 | 311 | 12981 |
Chi Hou Chan | 48 | 511 | 9504 |
Lin Shao | 48 | 380 | 12737 |
Johan Åkerman | 48 | 306 | 9814 |
Philip J. Tobin | 47 | 186 | 6502 |
Alexander A. Demkov | 47 | 331 | 7926 |