Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

Nonvolatile Memory Bitcell With Inlaid High K Metal Select Gate

Abstract: A process integration is disclosed for fabricating non-volatile memory (NVM) cells having recessed control gates ( 118, 128 ) on a first substrate area ( 111 ) which are encapsulated in one or more planar dielectric layers ( 130 ) prior to forming in-laid high-k metal select gates and CMOS transistor gates ( 136, 138 ) in first and second substrate areas ( 111, 113 ) using a gate-last HKMG CMOS process flow without interfering with the operation or reliability of the NVM cells.

Vertically formed neuron transister having a floating gate and a control gate

Abstract: A method for forming a vertical neuron MOSFET begins by providing a substrate (12). One or more conductive layers (24 and 28) are formed overlying the substrate (12). An opening (32) is formed through a portion of the conductive layers (24 and 28) to form one or more control electrodes from the conductive layers (24 and 28). A floating gate (36, and 38) is formed adjacent each of the control electrodes. A dielectric layer (34) is formed within the opening (32) and between the control electrodes and the floating gate (36, and 38) to provide for capacitive coupling between the control electrodes and the floating gate (36, and 38). The capacitive coupling may be altered for each control electrode via isotropic sidewall etching and other methods. By forming the neuron MOSFET in a vertical manner, a surface area of the neuron MOSFET is reduced when compared to known neuron MOSFET structures.

Microcontroller having an EPROM with a low voltage program inhibit circuit

Abstract: A microcontroller is provided having an on-chip electrically erasable programmable read-only-memory (EEPROM), which is user programmable via a programming register. The microcontroller includes a low voltage program inhibit (LVPI) circuit which is combined with the existing EEPROM design. By integrating the LVPI circuit into the EEPROM, the EEPROM may be protected without disabling the entire data processing system. If the supply voltage (V DD ) falls below a predetermined voltage level, the LVPI circuit inhibits the use of the EEPROM programming register, thereby preventing the CPU from programming or erasing the EEPROM. A comparator in the LVPI circuit compares a precision reference voltage to a voltage divided off of the power supply (V DD ), and provides a output signal to the EEPROM programming register. During normal operation, the comparator output signal is a logic low, which enables the user to program or erase the EEPROM, via the programming register. When the supply voltage is below the predetermined safe level, the comparator output signal is a logic high signal, which sets a control bit in the programming register. When set, the control bit clears the remaining bits in the programming register, thereby disabling a charge pump, and preventing any further EEPROM programming.

A varying pulse width 5 th -derivative gaussian pulse generator for UWB transceivers in CMOS

Abstract: A fully integrated, ultra low-power, varying pulse width fifth-order derivative Gaussian pulse generator designed and fabricated in a commercial 0.18 mum CMOS technology is reported for 3-10 GHz impulse ultra wideband (UWB) transceivers. The fifth-order derivative Gaussian pulse generator circuit consists of four parallel Gaussian pulse formation blocks and an output stage. It can generate UWB pulse signals with adjustable pulse width ranging from 240 picoseconds to a few nanoseconds. Measurement results show very short UWB pulses with amplitude of 51 mV and an ultra low power consumption of 3.6 mW at 100 MHz pulse repeating frequency (PRF) with 1.8 V power supply voltage. This pulse generator fully complies with FCC UWB power mask.

Programmable hash-tuple generation with parallel rule implementation independence

Abstract: Techniques have been developed to facilitate concurrent evaluation of hash rule entries in ways that allow an implementation to maintain a deterministic resultant hash irrespective of variations in the allocation of particular rules to particular storage banks or evaluation logic, such as may occur with rule set revisions. Similarly, uniform deterministic hash results can be assured even across a range of implementations that support greater or lesser levels of concurrent rule evaluations.