Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

Design of multiple-metal stacked inductors incorporating an extended physical model

Abstract: Modern analog circuits are heavily dependent on inductor performance, where the poor inductor quality factor (Q) of silicon processes leads to degradation in circuit efficacy, especially at RF and microwave frequencies. Several techniques have been proposed to enhance the Q of integrated on-chip inductors, but the most effective method of Q improvement is to lower the series resistance by increasing the inductor metal thickness. This paper presents the most cost-effective method of achieving a thick metal by using a standard 0.18-/spl mu/m multilayer BiCMOS process. An expanded physically based model for multiple-metal stacked inductors is presented, which expands on previous research to show the effects and limitations of stacking two, three, and four metal layers in a five-metal-layer process. The excellent accuracy of this geometrical model is illustrated with respect to a range of inductor designs showing that an improvement in Q of more than 50% may be achieved. Due to the increased parasitics in multilayer structures, the Q improvement is very frequency dependent, which is clearly predicted with the expanded model. The predictive capability of the model is further used to provide detailed insight into the effectiveness of a patterned ground shield for different substrate characteristics. This predictive ability will contribute greatly to first time right inductor designs and eliminate the expensive and time-consuming fabrication iterations required to fine tune other inductor models.

Multi-die semiconductor package

Abstract: A multi-die semiconductor package having an electrical interconnect frame. A top integrated circuit die is attached to the top side of an upper contact level of the frame and a bottom integrated circuit die is attached to the bottom side of the upper contact level of the frame. The die bond pads of the top die are electrically coupled (e.g. wired bonded) to pads of a lower contact level of the interconnect frame. The die bond pads of the bottom integrated circuit die are electrically coupled (e.g. wired bonded) to bond pads of the upper contact level of the frame. The bond pads of the lower contact level serve as external bond pads for the package. The frame may include inset structures, each having an upper portion located in the upper contact level and a lower portion located in the lower contact level.

Charge pump and control scheme

Abstract: A switch controller has a charge pump, a selector switch connected to the charge pump, and a pre-charge power supply input connectable to the input of the selector switch. For each of the output channels being controlled, a power control switch is connected to an output of the selector switch. In response to commands, output channels are enabled and disabled, causing corresponding actions in the power control switches. When an output channel is to be activated, the output channel is selected by the selector switch and the pre-charge power supply connected to the input of the selector switch. The charging is completed by the charge pump and the enabled status of the power control switch is maintained by the charge pump.

Micro-electro-mechanical systems device and integrated circuit device integrated in a three-dimensional semiconductor structure

Abstract: Semiconductor devices ( 300, 400 , and 500 ) including an integrated circuit (IC) device ( 100 ) coupled to a micro-electro-mechanical systems (MEMS) device ( 200 ) and a method ( 600 ) for producing same are disclosed. The IC device includes a die seal ring ( 130 ) and the MEMS device includes a MEMS seal ring ( 230 ), and the IC device is coupled to the MEMS device via the die seal ring and the MEMS seal ring. The MEMS device may include one or more passive devices ( 450, 475 ) coupled to it. Moreover, a substrate ( 510 ) including an aperture ( 550 ) may be coupled to the passive device, wherein the aperture enables the passive device to be trimmed after being disposed on the MEMS device. The semiconductor devices include an RF signal path ( 486 ) and at least one other signal path ( 482 and 484 ), wherein the other signal path(s) may be an analog and/or a digital signal path.

OPTIMIZED COMPRESSIVE SiGe CHANNEL PMOS TRANSISTOR WITH ENGINEERED Ge PROFILE AND OPTIMIZED SILICON CAP LAYER

Abstract: A semiconductor process and apparatus includes forming PMOS transistors (72) with enhanced hole mobility in the channel region by epitaxially growing a bi-axially stressed forward graded silicon germanium channel region layer (22) and a counter-doped silicon cap layer (23) prior to forming a PMOS gate structure (34) and associated source/drain regions (38, 40) in the channel region layer(s).