Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

Design-silicon timing correlation: a data mining perspective

Abstract: In the post-silicon stage, timing information can be extracted from two sources: (1) on-chip monitors and (2) delay testing. In the past, delay test data has been overlooked in the correlation study. In this paper, we take path delay testing as an example to illustrate how test data can be incorporated in the overall design-silicon correlation effort. We describe a path-based methodology that correlates measured path delays from the good chips, to the path delays predicted by timing analysis. We discuss how statistical data mining can be employed for extracting information and show experimental results to demonstrate the potential of the proposed methodology.

Process for preferentially etching polycrystalline silicon

Abstract: This disclosure relates to a process for etching polycrystalline silicon in preference to single crystal silicon. Polycrystalline silicon is anisotropically etched in a plasma which inclues a noncarbonaceus silicon etching compound such as chlorine together with about 0.4-1.5 percent by volume of oxygen. The process is used to fabricate semiconductor devices which require the etching of polycrystalline silicon in the presence of exposed monocrystalline silicon.

3-d inductor and transformer devices in mram embedded integrated circuits

Abstract: An integrated circuit device (300) includes a magnetic random access memory ('MRAM') architecture (310) and at least one inductance element (3 12, 3 14) formed on the same substrate using the same fabrication process technology. The inductance element, which may be an inductor or a transformer, is formed at the same metal layer (or layers) as the program lines of the MRAM architecture. Any available metal layer in addition to the program line layers can be added to the inductance element to enhance its efficiency. The concurrent fabrication of the MRAM architecture (310) and the inductance element (312, 314) facilitates an efficient and cost effective use of the physical space available over active circuit blocks of the substrate, resulting in three-dimensional integration.

Method of fabricating thermally stable mtj cell and apparatus

Abstract: An MTJ cell (50) including a tunneling layer (64) of material between magnetic material layers (62, 66) with the tunneling layer of material having a greater attraction for a third material than the magnetic material layers. The third material is introduced to one or both so that when the cell is heated the third material is redistributed from the magnetic material layer to the tunneling layer. Upon redistribution the tunneling layer becomes a tunnel barrier material. Also, a first diffusion barrier layer (67) is positioned between a first metal electrode (68) and one of the magnetic material layers (66) and/or a second diffusion barrier layer is positioned between a second metal electrode and the other magnetic material layer to prevent diffusion of the metal in the electrodes into the magnetic material layers.

Semiconductor wafer contact system and method for contacting a semiconductor wafer

Abstract: A semiconductor wafer contact system includes a base substrate (13) which has an array of raised supports (18). The array of raised supports (18) are distributed in a pattern corresponding to the pattern of electrical contacts (12) on the semiconductor wafer (10), to be contacted. In between the base substrate (13) and the wafer to be contacted (10) is a flexible circuit layer (14) including an array of electrical contacts (15) having the same pattern as the contacts (12) of the wafer and the raised supports (18). The raised supports (18) provide focused and localized force, pressing the membrane test contacts (15) against the wafer electrical contacts (12).