Institution
Freescale Semiconductor
About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..
Topics: Layer (electronics), Signal, Transistor, Integrated circuit, Voltage
Papers published on a yearly basis
Papers
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22 Feb 2007TL;DR: In this paper, a Controller Area Network (CAN) node consists of a high-powered microcontroller (10), a low standby power regulator (112), a CAN bus transceiver (106), and a minimal CAN message buffer for storing received messages.
Abstract: A Controller Area Network (CAN) node consists of a high-powered microcontroller (10), a low standby power regulator (112), a CAN bus transceiver (106), and a minimal CAN message buffer for storing received messages. Low power standby operation allows for the controller to power off, while the transceiver and regulator are operated in standby. The transceiver/regulator will enter run mode after the first symbol of a received CAN message is validated off the bus. As the original CAN message is received, it is buffered in the message buffer and, after stored, a status register is set to indicate the full message has been received. Once the controller has stabilized out of a wake-up mode, it retrieves the stored message and acts accordingly. The CAN message buffer is coupled to the controller by an system packet interface (SPI) interface (122) for transmission of a controller wake-up command and retrieval of a buffered message.
50 citations
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26 Nov 2014TL;DR: In this article, a resistive non-volatile memory cell is programmed and a programming voltage is applied to the first terminal of the resistive NVM cell, and the current through the NVM is limited to a second magnitude greater than the first magnitude.
Abstract: A resistive non-volatile memory cell is programmed. A programming voltage is applied to a first terminal of the resistive non-volatile memory cell. Sensing, during the applying the programming voltage, determines if the resistive non-volatile memory cell has been programmed. Current is limited through the resistive non-volatile memory cell to a first magnitude. After a predetermined time, if the sensing has not detected that the resistive non-volatile memory cell has been programmed, the current through the resistive non-volatile memory cell is limited to a second magnitude greater than the first magnitude. The resistive non-volatile memory cell is also erased.
50 citations
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02 Apr 1997TL;DR: In this paper, a monolithic integrated circuit die (10) is fabricated to include unilateral FETs (113, 114, 115), RF passive devices such as a double polysilicon capacitor (57), poly-silicon resistor (58), and inductor (155), and an ESD protection device (160).
Abstract: A monolithic integrated circuit die (10) is fabricated to include unilateral FETs (113, 114, 115), RF passive devices such as a double polysilicon capacitor (57), a polysilicon resistor (58), and an inductor (155), and an ESD protection device (160). A first P+ sinker (28) provides signal isolation between two FETs (113, 115) separated by the first sinker (28) and is coupled to a source region (86) of a power FET (115) via a self-aligned titanium silicide structure (96). A second P+ sinker (29) is coupled to a bottom plate (44) of the double polysilicon capacitor (57). A third P+ sinker (178) is coupled to a source region (168) of the ESD protection device (160) via another titanium silicide structure (174).
49 citations
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27 Aug 2001
TL;DR: A magneto-electronic component includes an electrically conductive layer for generating a magnetic field, a ferromagnetic cladding layer adjacent to the electrically-conductive layer, and an antiferromagnetic layer in this article.
Abstract: A magneto-electronic component includes an electrically conductive layer for generating a magnetic field, a ferromagnetic cladding layer adjacent to the electrically conductive layer, and an antiferromagnetic layer adjacent to the ferromagnetic cladding layer.
49 citations
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27 Sep 2007TL;DR: In this article, a method of packaging a first device having a first major surface and a second major surface is presented, where the first layer is selected from the group consisting of an encapsulant and a polymer.
Abstract: A method of packaging a first device having a first major surface and a second major surface includes forming a first layer over a second major surface of the first device and around sides of the first device and leaving the first major surface of the first device exposed, wherein the first layer is selected from the group consisting of an encapsulant and a polymer; forming a first dielectric layer over the first major surface of the first device, forming a via in the first dielectric layer, forming a seed layer within the via and over a portion of the first dielectric layer, physically coupling a connector to the seed layer, and plating a conductive material over the seed layer to form a first interconnect in the first via and over a portion of the first dielectric layer.
49 citations
Authors
Showing all 7673 results
Name | H-index | Papers | Citations |
---|---|---|---|
David Blaauw | 87 | 750 | 29855 |
Krishnendu Chakrabarty | 79 | 996 | 27583 |
Rajesh Gupta | 78 | 936 | 24158 |
Philippe Renaud | 77 | 773 | 26868 |
Min Zhao | 71 | 547 | 24549 |
Gary L. Miller | 63 | 306 | 13010 |
Paul S. Ho | 60 | 475 | 13444 |
Ravi Subrahmanyan | 59 | 353 | 14244 |
Jing Shi | 53 | 222 | 10098 |
A. Alec Talin | 52 | 311 | 12981 |
Chi Hou Chan | 48 | 511 | 9504 |
Lin Shao | 48 | 380 | 12737 |
Johan Åkerman | 48 | 306 | 9814 |
Philip J. Tobin | 47 | 186 | 6502 |
Alexander A. Demkov | 47 | 331 | 7926 |