Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

Multi-bit non-volatile memory device and method therefor

Abstract: A multi-bit non-volatile memory device includes a charge storage layer (14) sandwiched between two insulating layers (12 and 16) formed on a semiconductor substrate (10). A thick oxide layer (18) is formed over the charge storage layer (14) and a minimum feature sized hole is etched in the thick oxide layer (18). An opening is formed in the thick oxide layer (18). Side-wall spacers (60) formed on the inside wall of the hole over the charge storage layer have a void (62) between them that is less than the minimum feature size. The side-wall spacers (60) function to mask portions of the charge storage layer (14), when the charge storage layer is etched away, to form the two separate charge storage regions (55 and 57) under the side-wall spacers (60). The device can be manufactured using only one mask step. Separating the charge storage regions prevents lateral conduction of charge in the nitride.

Nonuniform Sampling of Periodic Bandlimited Signals

Abstract: Digital processing techniques are based on representing a continuous-time signal by a discrete set of samples. This paper treats the problem of reconstructing a periodic bandlimited signal from a finite number of its nonuniform samples. In practical applications, only a finite number of values are given. Extending the samples periodically across the boundaries, and assuming that the underlying continuous time signal is bandlimited, provides a simple way to deal with reconstruction from finitely many samples. Two algorithms for reconstructing a periodic bandlimited signal from an even and an odd number of nonuniform samples are developed. In the first, the reconstruction functions constitute a basis while in the second, they form a frame so that there are more samples than needed for perfect reconstruction. The advantages and disadvantages of each method are analyzed. Specifically, it is shown that the first algorithm provides consistent reconstruction of the signal while the second is shown to be more stable in noisy environments. Next, we use the theory of finite dimensional frames to characterize the stability of our algorithms. We then consider two special distributions of sampling points: uniform and recurrent nonuniform, and show that for these cases, the reconstruction formulas as well as the stability analysis are simplified significantly. The advantage of our methods over conventional approaches is demonstrated by numerical experiments.

Semiconductor device having a metal containing layer overlying a gate dielectric

Abstract: Metal semiconductor nitride gate electrodes (40, 70) are formed for use in a semiconductor device (60). The gate electrodes (40, 70) may be formed by sputter deposition, low pressure chemical vapor deposition (LPCVD), or plasma enhanced chemical vapor deposition (PECVD). The materials are expected to etch similar to silicon-containing compounds and may be etched in traditional halide-based etching chemistries. The metal semiconductor nitride gate electrodes (40, 70) are relatively stable, can be formed relatively thinner than traditional gate electrodes (40, 70) and work functions near the middle of the band gap for the material of the substrate (12).

Method for fabricating a semiconductor device having a planar surface

Abstract: A planar surface (24) is obtained in a semiconductor device (10) having regions of differing material composition by means of a non-selective planarization process. The non-selective planarization process removes insulating material and conductive material at substantially the same rate. In one embodiment of the invention, stud vias (22) are formed by the removal of portions of a conductive layer (20) overlying the surface of an interlevel dielectric layer (16). Once the conductive layer (20) has been removed, the planarization process is continued and surface portions of the interlevel dielectric layer (16) are also removed. Upon completion of the process a planar surface (24) is formed having regions of conductive material and insulating material.

Spur-Free Multirate All-Digital PLL for Mobile Phones in 65 nm CMOS

Abstract: We propose a new multirate architecture of an all-digital PLL (ADPLL) featuring phase/frequency modulation capability. While the ADPLL approach has already proven its benefits of power dissipation and cost reduction through the discrete-time operation and full RF-SoC integration in nanoscale CMOS, the coarse discretization of the phase detector function tends to keep it from reaching the ultimate of the RF performance potential. The proposed ADPLL features an arbitrarily high data rate modulation that is independent from the reference frequency. It is also made substantially free from injection pulling and ill-shaped quantization noise of the TDC by means of dithering with dynamic adjustment of differential pair mismatches as well as frequency translation of the feedback clock. Low power techniques, such as speculative clock retiming and asynchronous counter are used. The presented ADPLL is implemented in 65 nm CMOS as part of a single-chip GSM/EDGE RF-SoC. It occupies 0.35 mm2 and consumes 32 mA of current at 1.2 V supply in the low frequency band. The measured results show a virtually spur-free operation.